1. Field of the Invention
The present invention relates to a time to digital converter.
2. Description of the Related Art
A time to digital converter (hereinafter, “TDC”) is a device that performs measurement of decimal fraction time. In recent years, TDCs having accuracy of nano-second order to pico-second order can be easily realized by a CMOS circuit technology. An application range of the TDCs is extended to various fields. As one of applications of the TDCs, for example, as described in R. B. Staszewski and P. T. Balasare, “All-Digital Frequency Synthesizer in Deep-Submicron CMOS”, Wiley, New York, 2006, an all digital PLL (ADPLL) that is fully digitized by incorporating a TDC in a phase locked loop (hereinafter, “PLL”), digitization of which is advanced, is developed. The ADPLL has advantages that, for example, control of an operation state is easy, an analog loop filter is unnecessary, and an occupied area can be reduced by microminiaturization of a process.
The TDC used in the ADPLL captures outputs in respective delay stages of a delay circuit, to which an output signal of a digitally controlled oscillator (hereinafter, “DCO”) is input, in synchronization with a reference signal to convert a decimal fraction phase difference (time data) between a period of the output signal of the DCO and the reference signal into a digital code.
The ADPLL proposed in the past is assumed to be used in a radio circuit. An output frequency of the DCO is as high as several gigahertz order. Therefore, the TDC that detects decimal fraction phase information is used to set delay time to as short fixed time as possible and realize high time resolution of several pico-seconds.
However, the technology of the ADPLL proposed in the past does not indicate a clear guideline concerning a method of deciding the number of delay stages and delay time necessary for obtaining periodic data. Therefore, adjustment work for delay time of the TDC performed to acquire periodic data for each of DCOs in use is extremely bothersome.
For example, when it is attempted to apply a TDC to a low-frequency PLL such as a baseband PLL, if delay time of the TDC used in the ADPLL proposed in the past is applied to delay time of the TDC, it is necessary to increase the number of delay stages of the TDC to acquire periodic data of a low-frequency signal. Then, power consumption unnecessarily increases.
On the other hand, to prevent the problem, if a method of increasing a time delay amount of the delay stages of the delay circuit and acquiring periodic data of the low-frequency signal without increasing the number of delay stages of the delay circuit is adopted, when the time delay amount is too large, a waveform is dulled and the periodic data cannot be accurately acquired. As a result, a functional operation failure and a fall in resolution are caused.